A number of semiconductor devices are fabricated by epitaxially growing a number of semiconductor layers on a substrate. For example, one class of light emitting diodes (LEDs) is constructed by growing a number of epitaxially grown layers of GaN semiconductors on a substrate. The yield of devices from the fabrication process is reduced by defects in the epitaxially grown layers. One source of defects is the mismatch in the thermal expansion coefficients (TECs) between the epitaxially grown layers and the substrate. In the case of GaN semiconductors grown on sapphire, significant mismatches between both the thermal expansion coefficients and the lattice constants exist.
The mismatch is even greater for GaN semiconductor layers grown on silicon. As a result, the epitaxially grown layers tend to crack when the substrate and layers are cooled from the growth temperature. In addition, the GaN layers tend to bow during the growth process due to the thermal mismatch. This bowing interferes with the uniformity of the layers across the wafer.
Since silicon wafers offer significant advantages over sapphire wafers, a growth technique that reduces the stress caused by the TEC mismatch between the GaN based layers and the underlying substrate is needed.